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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4532CD647XFA
32M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE UNBUFFERED TYPE
Description
The MC-4532CD647XFA is 33,554,432 words by 64 bits synchronous dynamic RAM module on which 16 pieces of 128M SDRAM: PD45128841 are assembled. This module provides high density and large quantities of memory in a small space without utilizing the surfacemounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction.
Features
* 33,554,432 words by 64 bits organization * Clock frequency and access time from CLK.
Part number /CAS latency Clock frequency (MAX.) MC-4532CD647XFA-A75 CL = 3 CL = 2 133 MHz 100 MHz Access time from CLK (MAX.) 5.4 ns 6.0 ns
* Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Pulsed interface * Possible to assert random column address in every cycle * Quad internal banks controlled by BA0 and BA1 (Bank Select) * Programmable burst-length (1, 2, 4, 8 and full page) * Programmable wrap sequence (Sequential / Interleave) * Programmable /CAS latency (2, 3) * Automatic precharge and controlled precharge * CBR (Auto) refresh and self refresh * All DQs have 10 10 % of series resistor * Single 3.3 V 0.3 V power supply * LVTTL compatible * 4,096 refresh cycles/64 ms * Burst termination by Burst Stop command and Precharge command * 168-pin dual in-line memory module (Pin pitch = 1.27 mm) * Unbuffered type * Serial PD
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
Document No. E0230N20 (Ver 2.0) Date Published June 2002 (K) Japan URL: http://www.elpida.com
Elpida Memory, Inc. 2001-2002 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
MC-4532CD647XFA
Ordering Information
Part number Clock frequency (MAX.) MC-4532CD647XFA-A75 133 MHz 168-pin Dual In-line Memory Module (Socket Type) Edge connector: Gold plated 34.93 mm height 16 pieces of PD45128841G5 (Rev. X) (10.16 mm (400) TSOP (II)) Package Mounted devices
2
Data Sheet E0230N20 (Ver. 2.0)
MC-4532CD647XFA
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
/xxx indicates active low signal.
85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 VSS DQ32 DQ33 DQ34 DQ35 Vcc DQ36 DQ37 DQ38 DQ39 VSS DQ0 DQ1 DQ2 DQ3 Vcc DQ4 DQ5 DQ6 DQ7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
DQ40 DQ8 VSS VSS DQ41 DQ9 DQ42 DQ10 DQ43 DQ11 DQ44 DQ12 DQ45 DQ13 Vcc Vcc DQ46 DQ14 DQ47 DQ15 NC NC NC NC VSS VSS NC NC NC NC Vcc Vcc /WE /CAS DQMB0 DQMB4 DQMB1 DQMB5 /CS0 /CS1 NC /RAS VSS VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BA0 (A13) BA1 (A12) A11 Vcc Vcc CLK1 NC VSS CKE0 /CS3 DQMB6 DQMB7 NC Vcc NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 Vcc DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 Vcc DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 Vcc Vcc CLK0 VSS NC /CS2 DQMB2 DQMB3 NC Vcc NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 Vcc DQ20 NC NC CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 Vcc DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC NC SDA SCL Vcc
A0 - A11
: Address Inputs
[Row: A0 - A11, Column: A0 - A9] BA0 (A13), BA1 (A12) : SDRAM Bank Select DQ0 - DQ63 CLK0 - CLK3 CKE0, CKE1 /CS0 - /CS3 /RAS /CAS /WE SA0 - SA2 SDA SCL VCC VSS NC : Data Inputs/Outputs : Clock Input : Clock Enable Input : Chip Select Input : Row Address Strobe : Column Address Strobe : Write Enable : Address Input for EEPROM : Serial Data I/O for PD : Clock Input for PD : Power Supply : Ground : No Connection
DQMB0 - DQMB7 : DQ Mask Enable
Data Sheet E0230N20 (Ver. 2.0)
3
MC-4532CD647XFA
Block Diagram
/WE /CS0 DQMB0 /CS1 /CS2 DQMB2 /CS3
DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
DQMB1
DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D0 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D8 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23
DQMB3
DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D2 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D10 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15
DQMB4
DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D1 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D9 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31
DQMB6
DQ 4 DQM /CS DQ 7 DQ 6 DQ 5 D3 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 3 DQM /CS DQ 0 DQ 1 DQ 2 D11 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39
DQMB5
DQ 4 DQM DQ 7 DQ 6 DQ 5 DQ 3 DQ 2 DQ 1 DQ 0
/CS
/WE
DQ 3 DQM DQ 0 DQ 1 DQ 2 DQ 4 DQ 5 DQ 6 DQ 7
/CS
/WE
D4
D12
DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55
DQMB7
DQ 7DQM /CS DQ 6 DQ 5 DQ 4 D6 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D14 DQ 4 DQ 5 DQ 6 DQ 7
/WE
DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47
DQ 5 DQM DQ 7 DQ 6 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0
/CS
/WE
DQ 2 DQM DQ 0 DQ 1 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
/CS
/WE
D5
D13
DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
DQ 7 DQM /CS DQ 6 DQ 5 DQ 4 D7 DQ 3 DQ 2 DQ 1 DQ 0
/WE
DQ 0 DQM /CS DQ 1 DQ 2 DQ 3 D15 DQ 4 DQ 5 DQ 6 DQ 7
/WE
SERIAL PD SCL A0 A1 A2 SDA
CLK0
CLK: D0, D1, D4, D5
CLK2
CLK: D2, D3, D6, D7
3.3 pF
3.3 pF
CLK1
SA0 SA1 SA2
CLK: D8, D9, D12, D13 CLK3
CLK: D10, D11, D14, D15
3.3 pF
3.3 pF
A0 - A11 BA0, BA1 VCC C VSS
A0 - A11: D0 - D15 A13, A12: D0 - D15
/RAS /CAS
/RAS: D0 - D15 CKE1 /CAS: D0 - D15 CKE: D0 - D7
10 k CKE: D8-D15
D0 - D15 CKE0 D0 - D15
Remarks 1. The value of all resistors is 10 except CKE1. 2. D0 - D15: PD45128841 (4M words x 8 bits x 4 banks)
4
Data Sheet E0230N20 (Ver. 2.0)
MC-4532CD647XFA
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to GND Voltage on input pin relative to GND Short circuit output current Power dissipation Operating ambient temperature Storage temperature Symbol VCC VT IO PD TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 50 16 0 to 70 -55 to +125 Unit V V mA W C C
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Supply voltage High level input voltage Low level input voltage Operating ambient temperature Symbol VCC VIH VIL TA Condition MIN. 3.0 2.0 -0.3 0 TYP. 3.3 MAX. 3.6 VCC + 0.3 +0.8 70 Unit V V V C
Capacitance (TA = 25 C, f = 1 MHz)
Parameter Input capacitance Symbol CI1 CI2 CI3 CI4 CI5 Data input/output capacitance CI/O Test condition A0 - A11, BA0 (A13), BA1 (A12), /RAS, /CAS, /WE CLK0 - CLK3 CKE0, CKE1 /CS0 - /CS3 DQMB0 - DQMB7 DQ0 - DQ63 MIN. 36 20 28 15 5 7 TYP. MAX. 76 40 52 29 17 19 pF Unit pF
Data Sheet E0230N20 (Ver. 2.0)
5
MC-4532CD647XFA
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
-A75 Parameter Operating current Symbol ICC1 Burst length = 1 tRC tRC(MIN.), IO = 0 mA Precharge standby current in power down mode Precharge standby current in non power down mode ICC2P CKE VIL(MAX.), tCK = 15 ns Test condition
/CAS latency = 2 /CAS latency = 3
MIN.
MAX. 1,040 1,080 16 16 320
Unit mA
Notes 1
mA
ICC2PS CKE VIL(MAX.), tCK = ICC2N CKE VIH(MIN.), tCK = 15 ns, /CS VIH(MIN.), Input signals are changed one time during 30 ns.
mA
ICC2NS CKE VIH(MIN.), tCK = Input signals are stable. Active standby current in power down mode Active standby current in non power down mode ICC3P CKE VIL(MAX.), tCK = 15 ns
128 80 64 480 mA mA
ICC3PS CKE VIL(MAX.), tCK = ICC3N CKE VIH(MIN.), tCK = 15 ns, /CS VIH(MIN.), Input signals are changed one time during 30 ns. CKE VIH(MIN.), tCK = , Input signals are stable. tCK tCK(MIN.) IO = 0 mA ICC5 tRC tRC(MIN.)
/CAS latency = 2 /CAS latency = 3 /CAS latency = 2 /CAS latency = 3
ICC3NS Operating current (Burst mode) CBR (Auto) refresh current ICC4
320 1,200 1,480 2,080 2,160 32 - 16 + 16 +500 +3 mA mA 3 mA 2
Self refresh current Input leakage current
ICC6 II(L)
CKE 0.2 V VI = 0 to 3.6 V, All other pins not under test = 0 V CKE1
A
- 500 -3 2.4
Output leakage current High level output voltage Low level output voltage
IO(L) VOH VOL
DOUT is disabled, VO = 0 to 3.6 V IO = - 4.0 mA IO = + 4.0 mA
A
V
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
6
Data Sheet E0230N20 (Ver. 2.0)
MC-4532CD647XFA
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Test Conditions
Parameter AC high level input voltage / low level input voltage Input timing measurement reference level Transition time (Input rise and fall time) Output timing measurement reference level Value 2.4 / 0.4 1.4 1 1.4 Unit V V ns V
tCK tCH CLK 2.4 V 1.4 V 0.4 V tSETUP tHOLD 2.4 V 1.4 V 0.4 V tAC tOH Output tCL
Input
Data Sheet E0230N20 (Ver. 2.0)
7
MC-4532CD647XFA
Synchronous Characteristics
Parameter Symbol MIN. Clock cycle time /CAS latency = 3 /CAS latency = 2 Access time from CLK /CAS latency = 3 /CAS latency = 2 CLK high level width CLK low level width Data-out hold time Data-out low-impedance time Data-out high-impedance time /CAS latency = 3 /CAS latency = 2 Data-in setup time Data-in hold time Address setup time Address hold time CKE setup time CKE hold time CKE setup time (Power down exit) Command (/CS0 - /CS3, /RAS, /CAS, /WE, DQMB0 - DQMB7) setup time Command (/CS0 - /CS3, /RAS, /CAS, /WE, DQMB0 - DQMB7) hold time tCMH 0.8 ns tCK3 tCK2 tAC3 tAC2 tCH tCL tOH tLZ tHZ3 tHZ2 tDS tDH tAS tAH tCKS tCKH tCKSP tCMS 2.5 2.5 3.0 0 3.0 3.0 1.5 0.8 1.5 0.8 1.5 0.8 1.5 1.5 5.4 6.0 7.5 10 -A75 MAX. (133 MHz) (100 MHz) 5.4 6.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 1 1 Unit Note
Note 1. Output load
Z = 50 Output 50 pF
Remark These specifications are applied to the monolithic device.
8
Data Sheet E0230N20 (Ver. 2.0)
MC-4532CD647XFA
Asynchronous Characteristics
Parameter Symbol MIN. ACT to REF/ACT command period (operation) REF to REF/ACT command period (refresh) ACT to PRE command period PRE to ACT command period Delay time ACT to READ/WRITE command ACT(one) to ACT(another) command period Data-in to PRE command period Data-in to ACT(REF) command /CAS latency = 3 period (Auto precharge) Mode register set cycle time Transition time Refresh time (4,096 refresh cycles) /CAS latency = 2 tRC tRC1 tRAS tRP tRCD tRRD tDPL tDAL3 tDAL2 tRSC tT tREF 67.5 67.5 45 20 20 15 8 1CLK+22.5 1CLK+20 2 0.5 30 64 120,000 -A75 MAX. ns ns ns ns ns ns ns ns ns CLK ns ms 1 1 Unit Note
Note This device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125 MHz operation.
Data Sheet E0230N20 (Ver. 2.0)
9
MC-4532CD647XFA
Serial PD
Byte No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Function Described Defines the number of bytes written into serial PD memory Total number of bytes of serial PD memory Fundamental memory type Number of rows Number of columns Number of banks Data width Data width (continued) Voltage interface CL = 3 Cycle time CL = 3 Access time DIMM configuration type Refresh rate/type SDRAM width Error checking SDRAM width Minimum clock delay Burst length supported Number of banks on each SDRAM /CAS latency supported /CS latency supported /WE latency supported SDRAM module attributes SDRAM device attributes : General CL = 2 Cycle time Hex 80H 08H 04H 0CH 0AH 02H 40H 00H 01H 75H 54H 00H 80H 08H 00H 01H 8FH 04H 06H 01H 01H 00H 0EH A0H A0H 24 25-26 27 28 29 30 31 32 33 tRP(MIN.) tRRD(MIN.) tRCD(MIN.) tRAS(MIN.) Module bank density Command and address signal input setup time Command and address signal input hold time 34 35 36-61 62 63 64 SPD revision Checksum for bytes 0 - 62 Manufacture's JEDEC ID code Data signal input setup time Data signal input hold time 15H 08H 00H 12H B0H 10H 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 NEC 1.2 1.5 ns 0.8 ns CL = 2 Access time 60H 00H 14H 0FH 14H 2DH 20H 15H 08H Bit 7 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Bit 6 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bit 5 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 Bit 4 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 Bit 3 0 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 1 Bit 2 0 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 0 1 0 Bit 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 Bit 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 0 1 0 1 0 20 ns 15 ns 20 ns 45 ns 128M bytes 1.5 ns 0.8 ns 10 ns 10 ns 6 ns
(1/2)
Notes 128 bytes 256 bytes SDRAM 12 rows 10 columns 2 banks 64 bits 0 LVTTL 7.5 ns 5.4 ns None Normal x8 None 1 clock 1, 2, 4, 8, F 4 banks 2, 3 0 0
10
Data Sheet E0230N20 (Ver. 2.0)
MC-4532CD647XFA
(2/2)
Byte No. 65-71 72 73-90 91-92 93-94 95-98 Function Described Manufacture's JEDEC ID code Manufacturing location Manufacture's P/N Revision code Manufacturing date Assembly serial number Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Notes
99-125 Mfg specific 126 127 Intel specification frequency Intel specification /CAS latency support 64H FFH 0 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 100MHz
Timing Chart Refer to the PD45128441, 45128841, 45128163 Data sheet (E0031N).
Data Sheet E0230N20 (Ver. 2.0)
11
MC-4532CD647XFA
Package Drawing
Front side
Unit: mm
3.00 (DATUM -A-) (63.67) 4.80 Max
3.00
Component area (Front)
1 C 11.43 36.83 133.35 B 54.61 A 84
Back side 2 - 3.00
127.35
4.00
(DATUM -A-) Detail A
2.50 0.20
1.27 0.050
0.20 0.15
Detail B R FULL
Detail C (DATUM -A-) 1.00 R FULL
6.35
3.125 0.125
6.35
3.125 0.125
2.00 0.10
4.175 2.00 0.10
1.00 0.05
Note: Tolerance on all dimensions 0.15 unless otherwise specified.
ECA-TS2-0049-01
12
Data Sheet E0230N20 (Ver. 2.0)
34.93
Component area (Back)
17.80
4.00 Min
1.27
168
85
MC-4532CD647XFA
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Data Sheet E0230N20 (Ver. 2.0)
13
MC-4532CD647XFA
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations.
M01E0107

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